NEWS

VLSI Design and Verification: AMBA AXI4 & DDR4 Verification using System Verilog​-1 10 March 2025

Department of Electronics and Communication Engineering

Department of Electronics and Communication Engineering in association with RJ Semiconductors organising 5 days Hands on Workshop session on "VLSI Design and Verification: AMBA AXI4 & DDR4 Verification using System Verilog​-1"  for VI semester ECE students from 10/03/25 to 14/03/25.

Resource Persons: 1. Suraj G, Verification Engineer –I at Elobchip Electronics Pvt Ltd 
2. Amith Holi –RTL Design Engineer at Elobchip Electronics Pvt Ltd
3. Chandan K R, Senior Engineer –II at ST Micro electronics 

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